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high accuracy eprom programmable single-pll clock generato r cy2077 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 january 24, 2001 either features benefits ? high accuracy pll with 12-bit multiplier and 10-bit divider enables synthesis of highly accurate and stable output clock frequencies with zero ppm eprom-programmability enables quick turnaround of custom frequencies 3.3v or 5v operation supports industry standard design platforms operating frequency ? 390 khz?133 mhz at 5v ? 390 khz?100 mhz at 3.3v services most pc, networking, and consumer applications reference input from either a 10-30 mhz fundamental toned crystal or a 1-75 mhz external clock lowers cost of oscillator as pll can be programmed to a high frequency using either a low-frequency, low-cost crystal, or an existing system clock eprom-selectable ttl or cmos duty cycle levels duty cycle centered at 1.5v or v dd /2 provides flexibility to service most ttl or cmos applications sixteen selectable post-divide options, using either pll or reference oscillator/external clock provides flexibility in output configurations and testing programmable pwr_dwn or oe pin, with asynchro- nous or synchronous modes enables low-power operation or output enable function and flex- ibility for system applications, through selectable instantaneous or synchronous change in outputs low jitter outputs typically ? 80 ps at 3.3v/5v suitable for most pc, consumer, and networking applications controlled rise and fall times and output slew rate has lower emi than oscillators available in both commercial and industrial temperature suitable to fit most applications factory-programmable device options easy customization and fast turnaround. cy2077 logic block diagram xtalin pwr_dwn xtalout [1] configuration crystal clkout / 1, 2, 4, 8, 16, 32, 64, 128 oscillator or oe mux high accuracy pll eprom 1 2 3 4 5 8 7 6 vdd xtalout xtalin pd/oe vss clkout vss vss 8-pin top view q 10 bits p 12 bits phase detector charge pump vco note 1. when using an external clock source leave xtalout floating or external clock pin configuration
cy2077 2 functional description the cy2077 is an eprom-programmable, high-accuracy, general purpose, pll-based design for use in applications such as modems, disk drives, cd-rom drives, video cd play- ers, dvd players, games, set-top boxes, and data/telecommu- nications. the cy2077 can generate a clock output up to 133 mhz at 5v or 100 mhz at 3.3v. it has been designed to give the customer a very accurate and stable clock frequency with little to zero ppm error. the cy2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design specifi- cations. further more, there are 8 output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. the output divider can select between the pll and crystal oscillator output/external clock, providing a total of 16 different options. to add more flexibility in designs. ttl or cmos duty cycles can be selected. power management with the cy2077 is also very flexible. the user may choose either a pwr_dwn or an oe feature with which both have integrated pull-up resistors. pwr_dwn and oe signals can be programmed to have asynchronous and synchronous timing with respect to the output siginal. there is a weak pull-down on the output that will pull clkout low when either the pwr_dwn or oe siginal is active. this weak pull-down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path. multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the cy2077 to be used in applications which require low jitter and accurate reference frequencies. eprom configuration block ta b l e 1 summarizes the features which are configurable by eprom . pll output frequency the cy2077 contains a high resolution pll with 12 bit multi- plier and 10 bit divider.the output frequency of the pll is de- termined by the following formula: where p is the feedback counter value and q is the reference counter value. p and q are eprom programmable values. the calculation of p and q values for a given pll output fre- quency is handled by the cyclocks software. refer to the ?custom configuration request procedure? section for details. power management features pwr_dwn and oe options are configurable by eprom pro- gramming for the cy2077. in pwr_dwn mode, all active cir- cuits are powered down when the control pin is set to low. when the control pin is set back to high, both the pll and oscillator circuit must re-lock. in the case of oe, the output is three-stated and weakly pulled down when the control pin is set to low. the oscillator and pll are still active in this state, which leads to a quick clock output return when the control pin is set back to high. additionally, pwr_dwn and oe can be configured to occur asynchronously or synchronously with respect to clkout. in asynchronous mode, pwr_dwn or oe disables clkout im- mediately (allowing for logic delays), without respect to the cur- rent state of clkout. synchronous mode will prevent output glitches by waiting for the next falling edge of clkout after pwr_dwn or oe becomes asserted. in either asynchronous or synchronous setting, the output is always enabled synchro- nously by waiting for the next falling edge of clkout. table 1. eprom adjustable features eprom adjustable features adjust freq. feedback counter value (p) reference counter value (q) output divider selection duty cycle levels (ttl or cmos) power management mode (oe or pwr_dwn) power management timing (synchronous or asynchronous) f pll 2p5 + () ? q2 + () --------------------------- f ref ? = pin summary name pin description v dd 1 voltage supply. v ss 5,6,7 ground (all the pins have to be grounded). x d 2 crystal output (leave this pin floating when external reference is used.). x g 3 crystal input or external input reference. pwr_dwn / oe 4 eprom programmable power down or output enable pin. weak pull-up. clkout 8 clock output. weak pull-down.
cy2077 3 absolute maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage ..................................................?0.5 to +7.0v input voltage ............................................?0.5v to v dd +0.5v storage temperature (non-condensing) ... ?55c to +150c junction temperature .................................................. 150c static discharge voltage .......................................... > 2000v (per mil-std-883, method 3015) device functionality: output frequencies symbol description condition min. max. unit fo output frequency v dd = 4.5?5.5v 0.39 133 mhz v dd = 3.0?3.6v 0.39 100 mhz operating conditions for commercial temperature device parameter description min. max. unit v dd supply voltage 3.0 5.5 v t a operating temperature, ambient 0 +70 c c ttl max. capacitive load on outputs for ttl levels v dd = 4.5?5.5v, output frequency = 1?40 mhz v dd = 4.5?5.5v, output frequency = 40?125 mhz v dd = 4.5?5.5v, output frequency = 125?133 mhz 50 25 15 pf pf pf c cmos max. capacitive load on outputs for cmos levels v dd = 4.5?5.5v, output frequency = 1?40 mhz v dd = 4.5?5.5v, output frequency = 40?125 mhz v dd = 4.5?5.5v, output frequency = 125?133 mhz v dd = 3.0?3.6v, output frequency = 1?40 mhz v dd = 3.0?3.6v, output frequency = 40?100 mhz 50 25 15 30 15 pf pf pf pf pf x ref reference frequency, input crystal with c load = 10 pf 10 30 mhz reference frequency, external clock source 1 75 mhz electrical characteristics t a = 0 c to +70 c parameter description test conditions min. typ. max. unit v il low-level input voltage v dd = 4.5?5.5v v dd = 3.0?3.6v 0.8 0.2v dd v v v ih high-level input voltage v dd = 4.5?5.5v v dd = 3.0?3.6v 2.0 0.7v dd v v v ol low-level output voltage v dd = 4.5?5.5v, i ol = 16 ma v dd = 3.0?3.6v, i ol = 8 ma 0.4 0.4 v v v ohcmos high-level output voltage, cmos levels v dd = 4.5?5.5v, i oh = ?16 ma v dd = 3.0?3.6v, i oh = ?8 ma v dd ?0.4 v dd ?0.4 v v v ohttl high-level output voltage, ttl levels v dd = 4.5?5.5v, i oh = ?8 ma 2.4 v i il input low current v in = 0v 10 a i ih input high current v in = v dd 5 a i dd power supply current, unloaded v dd = 4.5?5.5v, output frequency <= 133 mhz v dd = 3.0?3.6v, output frequency <= 100 mhz 45 25 ma ma i dds stand-by current (pd = 0) v dd = 4.5-5.5v v dd = 3.0-3.6v 25 10 100 50 a r up input pull-up resistor v dd = 4.5?5.5v, v in = 0v v dd = 4.5?5.5v, v in = 0.7v dd 1.1 50 3.0 100 8.0 200 m ? k ? i oe_clkout clkout pulldown current v dd =5.0 20 a note: 1. when using cyclocks, please note that the pll frequency range is from 50 mhz to 250 mhz for 5v v dd supply, and 50 mhz to 180 mhz for 3v v dd supply. the output frequency is determined by the selected output divider.
cy2077 4 output clock switching characteristics commercial over the operating range [2] parameter description test conditions min. typ. max. unit t 1w output duty cycle at 1.4v, v dd = 4.5?5.5v t 1w = t 1a t 1b 1?40 mhz, c l <= 50 pf 40?125 mhz, c l <= 25 pf 125?133 mhz, c l <= 15 pf 45 45 45 55 55 55 % % % t 1x output duty cycle at v dd /2, v dd = 4.5?5.5v t 1x = t 1a t 1b 1?40 mhz, c l <= 50 pf 40?125 mhz, c l <= 25 pf 125?133 mhz, c l <= 15 pf 45 45 45 55 55 55 % % % t 1y output duty cycle at v dd /2, v dd = 3.0?3.6v t 1y = t 1a t 1b 1?40 mhz, c l <= 30 pf 40?100 mhz, c l <= 15 pf 45 40 55 60 % % t 2 output clock rise time between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 50 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 25 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 15 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v?5.5v, c l = 50 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 30 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 15 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 3 output clock fall time between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 50 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 25 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 15 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v-5.5v, c l = 50 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 30 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 15 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 4 start-up time out of power-down pwr_dwn pin low to high [3] 12ms t 5a power down delay time (synchronous setting) pwr_dwn pin low to output low (t=period of output clk) t/2 t+10 ns t 5b power down delay time (asynchronous setting) pwr_dwn pin low to output low 10 15 ns t 6 power up time from power-on [1] 12ms t 7a output disable time (synchronous setting) oe pin low to output hi-z (t=period of output clk) t/2 t+10 ns t 7b output disable time (asynchronous setting) oe pin low to output hi-z 10 15 ns t 8 output enable time (always synchronous enable) oe pin low to high (t=period of output clk) t1.5t +25n s ns t 9 peak-to-peak period jitter v dd =3.0v?3.6v, 4.5v?5.5v, fo>33 mhz, vco>100 mhz v dd = 3.0v?5.5v, fo <33 mhz 80 0.3 % 150 1% ps % of f o notes: 2. not all parameters measured in production testing. 3. oscillator start time cannot be guaranteed for all crystal types. this specification is for operation with at cut crystals wi th esr < 70 ? .
cy2077 5 operating conditions for industrial temperature device parameter description min. max. unit v dd supply voltage 3.0 5.5 v t a operating temperature, ambient ?40 +85 c c ttl max. capacitive load on outputs for ttl levels v dd = 4.5?5.5v, output frequency = 1?40 mhz v dd = 4.5?5.5v, output frequency = 40?125 mhz v dd = 4.5?5.5v, output frequency = 125?133 mhz 35 15 10 pf pf pf c cmos max. capacitive load on outputs for cmos levels v dd = 4.5?5.5v, output frequency = 1?40 mhz v dd = 4.5?5.5v, output frequency = 40?125 mhz v dd = 4.5?5.5v, output frequency = 125?133 mhz v dd = 3.0?3.6v, output frequency = 1?40 mhz v dd = 3.0?3.6v, output frequency = 40?100 mhz 35 15 10 20 10 pf pf pf pf pf x ref reference frequency, input crystal with c load = 10 pf 10 30 mhz reference frequency, external clock source 1 75 mhz electrical characteristics t a = ?40 c to +85 c parameter description test conditions min. typ. max. unit v il low-level input voltage v dd = 4.5?5.5v v dd = 3.0?3.6v 0.8 0.2v dd v v v ih high-level input voltage v dd = 4.5?5.5v v dd = 3.0?3.6v 2.0 0.7v dd v v v ol low-level output voltage v dd = 4.5?5.5v, i ol = 16 ma v dd = 3.0?3.6v, i ol = 8 ma 0.4 0.4 v v v ohcmos high-level output voltage, cmos levels v dd = 4.5?5.5v, i oh = ?16 ma v dd = 3.0?3.6v, i oh = ?8 ma v dd ?0.4 v dd ?0.4 v v v ohttl high-level output voltage, ttl levels v dd = 4.5?5.5v, i oh = ?8 ma 2.4 v i il input low current v in = 0v 10 a i ih input high current v in = v dd 5 a i dd power supply current, unloaded v dd = 4.5?5.5v, output frequency <= 133 mhz v dd = 3.0?3.6v, output frequency <= 100 mhz 45 25 ma ma i dds stand-by current (pd = 0) v dd = 4.5-5.5v v dd = 3.0-3.6v 25 10 100 50 a r up input pull-up resistor v dd = 4.5?5.5v, v in = 0v v dd = 4.5?5.5v, v in = 0.7v dd 1.1 50 3.0 100 8.0 200 m ? k ? i oe_clkout clkout pulldown current v dd =5.0 20 a
cy2077 6 output clock switching characteristics industrial over the operating range [3] parameter description test conditions min. typ. max. unit t 1w output duty cycle at 1.4v, v dd = 4.5?5.5v t 1w = t 1a t 1b 1?40 mhz, c l <= 35 pf 40?125 mhz, c l <= 15 pf 125?133 mhz, c l <= 10 pf 45 45 45 55 55 55 % % % t 1x output duty cycle at v dd /2, v dd = 4.5?5.5v t 1x = t 1a t 1b 1?40 mhz, c l <= 35 pf 40?125 mhz, c l <= 15 pf 125?133 mhz, c l <= 10 pf 45 45 45 55 55 55 % % % t 1y output duty cycle at v dd /2, v dd = 3.0?3.6v t 1y = t 1a t 1b 1?40 mhz, c l <= 20 pf 40?100 mhz, c l <= 10 pf 45 40 55 60 % % t 2 output clock rise time between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 35 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 15 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 10 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v?5.5v, c l = 35 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 20 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 10 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 3 output clock fall time between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 35 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 15 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 10 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v-5.5v, c l = 35 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 20 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 10 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 4 start-up time out of power-down pwr_dwn pin low to high [1] 1 2 ms t 5a power down delay time (synchronous setting) pwr_dwn pin low to output low (t=period of output clk) t/2 t+10 ns t 5b power down delay time (asynchronous setting) pwr_dwn pin low to output low 10 15 ns t 6 power up time from power on [1] 1 2 ms t 7a output disable time (synchronous setting) oe pin low to output hi-z (t=period of output clk) t/2 t+10 ns t 7b output disable time (asynchronous setting) oe pin low to output hi-z 10 15 ns t 8 output enable time (always synchronous enable) oe pin low to high (t=period of output clk) t 1.5t+ 25ns ns t 9 peak-to-peak period jitter v dd =3.0v?3.6v, 4.5v?5.5v, fo>33 mhz, vco>100 mhz v dd = 3.0v?5.5v, fo <33 mhz 80 0.3 % 150 1% ps % of f o switching waveforms duty cycle timing (t 1w, t 1x, t 1y ) t 1a t 1b output
cy2077 7 notes: 4. in synchronous mode the power-down or output three-state is not initiated until the next falling edge of the output clock. 5. in asynchronous mode the power-down or output three-state occurs within 25 ns irrespective of position in the ouput clock cyc le. switching waveforms (continued) output rise/fall time output t 2 v dd 0v t 3 power down timing (synchronous and asynchronous modes) clkout v dd t 4 1/f t 5a v il v ih power down 0v 1/f t 5b clkout t (synchronous [4 ] ) (asynchronous [5 ] ) power up timing clkout v dd t 6 1/f v dd -10% power up 0v min 2 ns clkout v dd output enable 0v output enable timing (synchronous and asynchronous modes) v il t 7a t 8 high impedance clkout t 7b t 8 high impedance t (synchronous [4 ] ) (asynchronous [5 ] ) v ih
cy2077 8 ordering information custom configuration request procedure the cy2077 is an eprom-programmable device that is configured in the factory. the output frequencies requested will be matched as closely as the internal pll divider and multiplier options allow. all custom requests must be submitted to your loca l cypress field application engineer (fae) or sales representative. the method to use to request custom configurations is: use cyclocks? software of version 3.65 or greater. this software automatically calculates the output frequencies that can be generated by the cy2077 devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local fae or sales representative. the cyclocks software is available free of charge from the cypress website (http://www.cypress.com) or from your local sales representative. once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., cy2077sc-103) specific to the frequencies and pinout of your device. this will be the part number used for samples requests and production orders. ordering code type operating range cy2077sc-xxx soic commercial cy2077zc-xxx tssop commercial CY2077SI-XXX soic industrial cy2077zi-xxx tssop industrial
cy2077 9 typical rise time [6] and fall time [6] trends for cy2077 rise/fall time vs. v dd over temperatures rise/fall time vs. output loads over temperatures ris e tim e vs . v dd -- cm os du ty cycle cload = 15pf 1.00 1.20 1.40 1.60 1.80 2.00 2.7 3.0 3.3 3.6 3.9 v dd (v ) rise time (ns) -40c 25c 85c fall tim e vs. vdd -- cm os duty cycle cload = 15pf 1.00 1.20 1.40 1.60 1.80 2.00 2.7 3.0 3.3 3.6 3.9 vdd (v) fall time (ns) -40c 25c 85c ris e tim e vs . v dd -- tt l d ut y cycle cload = 15pf 0.20 0.30 0.40 0.50 0.60 0.70 4.0 4.5 5.0 5.5 6.0 v dd (v ) rise time (ns) -40c 25c 85c fall tim e vs. vdd -- ttl duty cycle cload = 15pf 0.20 0.30 0.40 0.50 0.60 0.70 4.0 4.5 5.0 5.5 6.0 vdd (v) fall time (ns) -40c 25c 85c rise tim e vs. cload over tem perature vdd = 3.3v, cmos output 1.00 1.20 1.40 1.60 1.80 2.00 2.20 10 15 20 25 30 35 cload (pf) rise time (ns) -40c 25c 85c fall tim e vs. cload over tem perature v dd = 3.3v, cm os output 1.00 1.20 1.40 1.60 1.80 2.00 10 15 20 25 30 35 cload (pf) fall time (ns) -40c 25c 85c note: 6. rise/fall time for cmos output is measured between 1.2 v dd and 0.8 v dd . rise/fall time for ttl output is measured between 0.8v and 2.0v.
cy2077 10 typical duty cycle [7] trends for cy2077 duty cycle vs. output frequency over temperatures duty cycle vs. output load duty cycle vs. v dd over temperatures duty cycle vs. vdd over tem perature (ttl duty cycle output, fout=50mhz, cload = 50pf) 45.00 47.00 49.00 51.00 53.00 55.00 4.0 4.5 5.0 5.5 6.0 vdd (v) duty cycle (%) -40c 25c 85c duty cycle vs. vdd over tem perature (cmos duty cycle ouput, fout=50mhz, cload=50pf) 45.00 47.00 49.00 51.00 53.00 55.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd ( v) duty cycle (%) -40c 25c 85c duty cycle vs. cload w ith various vdd (fout = 50mhz, temp = 25c) 45.00 47.00 49.00 51.00 53.00 55.00 10 15 20 25 30 35 40 45 50 55 cload (pf) duty cycle (%) vdd=4.5v vdd=5.0v vdd=5.5v output duty cycle vs. fout over tem perature (vdd = 5v, cload = 15pf) 50.00% 51.00% 52.00% 53.00% 54.00% 55.00% 20 30 40 50 60 70 80 output frequency (mhz) output dc (%) 25c 85c -40c note: 7. duty cycle is measured at 1.4v for ttl output and 0.5 v dd for cmos output.
cy2077 11 period jitter (pk-pk) vs. vdd over temperatures (fout=40mhz, cload = 30pf) 0 20 40 60 80 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) period jitter (ps) -40c 25c 85c output jitter (pk-pk) vs. output frequency (vdd=3.3v, cload=15pf , cmos output) 0 20 40 60 80 10 0 0 20406080100120140 output frequency (mhz) jitter (ps) 25c -4 0 c 85c output jitter(pk-pk) vs. output frequency (vdd=5.0v, cload=15pf , cmos output) 0 20 40 60 80 1 00 0 204060801 00 1 20 1 40 output frequency (mhz) jitter (ps) 25c - 40c 85c typical jitter trends for cy2077 period jitter (pk-pk) vs. v dd over temperatures period jitter (pk-pk) vs. output frequency over temperatures
cy2077 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. document #: 38-01009-*b 8-lead (150-mil) soic s8 51-85093 8-lead thin shrunk small outline package (4.40 mm body) z8 package diagrams

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